1. Field of the Invention
The invention relates to flash memories, and more particularly to flash memory controllers.
2. Description of the Related Art
A flash memory needs a driving current to drive the operation thereof. Ordinarily, a driving current for a flash memory is provided by a flash memory controller. The flash memory controller provides a driving current with a constant level to drive flash memories. Because a single flash memory stores a limited amount of data, an electronic apparatus with an increased data capacity comprises more then one flash memory controlled by a single flash memory controller.
To increase data capacity of an electronic apparatus, the total number of flash memories controlled by a flash memory controller is increased. Referring to FIG. 1, a schematic diagram of a flash memory controller 102 controlling a plurality of flash memories is shown. The driving current provided by the flash memory controller 102 must maintain the data-access operations of eight flash memories 111˜118. Because the flash memory controller 102 merely provides a driving current with a constant level, and the driving current is shared between the flash memories 111˜118, each flash memory only obtains a portion of the driving current. When the total number of the flash memories controlled by the flash memory controller 102 is less than four, the driving current provided by the flash memory controller 102 can ensure correctness of the data-access operations of the flash memories. When the total number of the flash memories controlled by the flash memory controller 102 is greater than four, the level of the driving current obtained by each flash memory cannot maintain correctness of data-access operations, and errors are introduced into the data-access operations.
Referring to FIG. 2A, a schematic diagram of a data signal output by a flash memory driven by a driving current with an appropriate level is shown. When the flash memory is driven by a driving current with an appropriate level, the rising time of a data signal output by the flash memory is 1.2 ns, and the amplitude of the data signal is 3.3V. When the flash memory is driven by a driving current with an insufficient level, the driving current cannot provide enough power to the flash memory, and the data signal output by the flash memory has a high attenuation and a high noise level. Referring to FIG. 2B, a schematic diagram of a data signal output by a flash memory driven by a driving current with an insufficient level is shown. When the flash memory is driven by a driving current with an insufficient level, the rising time of a data signal output by the flash memory is lengthened to 4.45 ns, and the amplitude of the data signal is reduced to 2.8V. Errors are therefore easily introduced into the data-access operations of the flash memories. To maintain correctness of the data-access operations of the flash memory, a driving current with an appropriate level is therefore required. A flash memory controller capable of generating a driving current with an appropriate level is therefore required.